A) Field
The embodiments discussed herein are related to a semiconductor device including a high voltage transistor and its manufacture method. A transistor having a gate insulating film under a gate electrode is called broadly a MOS transistor.
B) Related Art
In a semiconductor integrated circuit, in addition to a MOS transistor called a core MOS transistor, it becomes necessary in some cases to use another MOS transistor operating at a voltage higher than that of the core MOS transistor. If an input/output voltage of an external circuit is about 3.5 V, an input/output MOS transistor operating at about 3.5 V is required, and in other cases, a MOS transistor operating at a higher operation voltage is required.
In a power amplifier transistor mounted on a transmission module of a wireless portable apparatus, a drain output voltage swings generally a two-fold of a bias voltage or more, in response to an input radio frequency (RF) power. A MOS transistor is therefore required to have a high drain breakdown voltage. A power amplifier mounted on a portable apparatus is generally used in a several hundreds MHz to several GHz band. Excellent high frequency characteristics are therefore desirable at the same time. In high output and high frequency power amplifiers, which are not limited to portable apparatus, high breakdown voltage and excellent high frequency characteristics are often desirable.
For a MOS transistor having high breakdown voltage and excellent high frequency characteristics, it is desired to lower an on-resistance and improve a gain at high frequency. A high breakdown voltage can be obtained by widening a depletion layer between an effective channel region, where current is controlled by a gate voltage, and the drain region connected to a drain electrode. An LDD structure having a region of a lower impurity concentration than that of the drain region (i.e., lightly doped drain (LDD)) formed between the drain region and gate electrode is used widely in MOS transistors.
A structure effective for realizing a high breakdown voltage is an extended drain (ED) MOS transistor structure which widens a depletion layer under the influence of gate voltage, by elongating an overlap length between the LDD region and gate electrode.
It is necessary to secure a threshold voltage and prevent punch-through even in a state of a widened depletion layer. When an impurity concentration in the channel region is increased, it is effective for securing a threshold voltage and preventing punch-through. However, when the channel impurity concentration is increased uniformly, an on-resistance is likely to be raised. Laterally modulated impurity distribution obtained by modulating the lateral distribution of a channel impurity concentration so as to lower the concentration toward the drain makes it possible to secure a threshold voltage in high impurity concentration region and accelerate carriers by built-in field by the impurity concentration gradient. This results in a lowered on-resistance of a MOS transistor and improvement in a high frequency output power. A laterally diffused (LD) channel MOS transistor structure formed by doping channel impurities at a source side region and thermally diffusing the impurities in lateral direction toward the drain side can realize the structure that channel impurities are gradually reduced from the source side to the drain side. In order to diffuse impurities by a long distance, however, it becomes necessary to adopt a high temperature and long time annealing process.
There is difficulty in forming an LDMOS transistor on the same chip as that of a fine MOS transistor of the 90 nm generation and following generations. In addition, a source side resistance is likely to become high if a channel impurity concentration is increased at the source side.
F.-C. HSU et al.: IEEE ED EDL 5, No. 3, pp. 71-74 (1984) reports that in a MOSFET of a novel structure including a minimum overlap gate, an offset gate, a concentration gradient drain, an LDD structure and the like, interface charges induced by hot carrier injection in a low sheet-charge density region outside the gate edge causes an external channel pinch-off so that a transconductance is likely to lower (degrade) considerably, and describes that since degradation is very sensitive to a sheet-charge density outside the gate edge, an overlap should be provided between the gate electrode and the source/drain region.
Japanese Patent Laid-open Publication No. 10-116983 indicates that since a p-type well for a medium or middle voltage MOS transistor has a high concentration for the purpose of a short channel, this MOS transistor is not suitable for a high voltage MOS transistor whose p-type well has preferably a low concentration for high breakdown voltage, and proposes that n-type impurity ions As are implanted into a region near the drain, by using resist mask, and p-type impurity ions B are implanted broadly in the active region in an n-type silicon substrate, and the impurity ions are diffused at the same time by thermal diffusion of, e.g., at 1200° C., for 8 hours to form a very low concentration p−-type diffusion layer in a p-type well lowering its effective impurity concentration through compensation by n-type impurities, and that n-type impurity ions, e.g., P ions, are implanted into the p−-type diffusion layer and diffused by thermal diffusion of 1200° C. and 2 hours to form an n−-type drain (LDD) diffusion layer. Thereafter, a gate electrode is formed overlapping the n−-type drain diffusion layer, and an n+-type drain region is formed spaced apart from the gate electrode.
Japanese Patent Laid-open Publication No. 2002-261276 indicates that when avalanche multiplication occurs in an NMOS transistor having an n-type drain with an LDD region formed in a p-type substrate, a substrate potential may rise because of inflow of positive charges, forming a parasitic bipolar transistor, and positive feed-back may occur, and proposes that a gate electrode is formed overlapping the LDD region, a high concentration drain region is formed being separated from the edge of the gate electrode on the drain side, and a middle concentration drain region is formed extending from a neighborhood of the gate electrode to the high concentration drain region, the impurity concentration lowering from the gate electrode side toward the high concentration drain region. The middle concentration drain region formed by ion implantation at a high acceleration energy, has an impurity concentration peak at a predetermined depth, and lowers its impurity concentration toward the surface.